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[AKD4371-B]
AKD4371-B
AK4371 Evaluation Board Rev.1
GENERAL DESCRIPTION The AKD4371 is an evaluation board for 24bit DAC with Headphone Amplifier, AK4371. The AKD4371 has the interface with AKM's ADC evaluation boards. Therefore, it's easy to evaluate the AK4371. The ADK4370 also has the digital audio interface and can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD4371-B --Evaluation board for AK4371 (Cable for connecting with printer port of IBM-AT compatible PC and control software are packed with this. This control software does not operate on Windows NT.)
FUNCTION * Compatible with 2 types of interface - Direct interface with AKM's A/D converter evaluation boards - On-board AK4116 as DIR which accepts optical input * 10pin header for serial control interface * Mini-jack for external Stereo Speaker * On-board Class-D Speaker Amplifier (AK7832)
Vcc (5.0V)
Regulator (3.3V)
Opt In (PORT1) DSP 10pin Header (PORT2)
GND
MOUT
HPL HPR
AK4116 (DIR)
HP
AK4371
AK7832
(SPK-Amp)
SPPL SPPR
Control Data 10pin Header (PORT3)
LIN1 RIN1
LIN2 RIN2
LIN3 RIN3
LOUT ROUT L/ROUT
Figure 1. AKD4371 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
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Evaluation Board Manual Operation sequence
1) Set up the power supply lines. [VCC] (red) = 5.0V : for Regulator [AGND] (black) = 0V : for analog ground [DGND] (black) = 0V : for logic ground Each supply line should be distributed from the power supply unit. 3.3V is supplied to AK4371 via the regulator. 2) Set up the evaluation mode, jumper pins. (See the followings.) 3) Power on. The AK4371 and AK4116 should be resets once bringing SW1(DAC/DIR_PDN) "L" upon power-up. And the AK7832 should be resets once bringing SW2(SPK_PDN) "L" upon power-up.
Evaluation mode
When evaluating the AK4371 using the PORT1(AK4116), it is possible to use the initial setting of the audio interface format (24bit MSB justified). The AK4116 operates at fs of 32kHz or more. If the fs is slower than 32kHz, any other evaluation mode should be used. When inputting the data from the PORT2, the AK4371's audio interface format should be set to correspond the input data's audio interface format. Refer to the AK4371's datasheet. Applicable Evaluation Mode (1) PLL Master Mode (2) PLL Slave Mode (2-1) PLL Reference Clock : MCKI pin (2-2) PLL Reference Clock : BICK or LRCK pin (3) External Slave Mode (3-1) Evaluation using DIR (Optical Link) of AK4116 (3-2) Evaluation connecting AKD4371 with external DSP (4) External Master Mode
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(1) PLL Master Mode PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR). BICK and LRCK are supplied from PORT2.It is possible to evaluate at various sampling frequencies using built-in the AK4371's PLL.
27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz
AK4371
MCKI MCKO BICK LRCK SDATA
DSP or P
256fs/128fs/64fs/32fs 32fs, 64fs 1fs
MCLK BCLK LRCK SDTO
Figure 2. PLL Master Mode
The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of DSP. The JP3(LRCK2) and JP4(BICK2)'s right side should be connected to LRCK and BICK of DSP. In case of supplying MCKO to DSP, the test pin(MCKO) should be connected to MCLK of DSP. Set up the jumper pins.
JP3 LRCK2
JP4 BICK2
JP5 MCLK
JP6 BICK
JP7 LRCK
JP8 SDTO
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(2) PLL Slave Mode
(2-1) PLL Reference Clock : MCKI pin
AK4371
MCKI MCKO BICK LRCK SDATA
27MHz,26MHz,19.8MHz,19.68MHz, 19.2MHz,15.36MHz,14.4MHz,13MHz, 12MHz,11.2896MHz
DSP or P
256fs/128fs/64fs/32fs 32fs ~ 64fs 1fs
MCLK BCLK LRCK SDTO
Figure 3. PLL Master Mode (PLL Reference Clock : MCKI pin)
PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR). MCKO is needed for a synchronous signal of BICK and LRCK. MCLK,BICK,LRCK and SDATA are supplied from PORT2. The test pin(MCKO) should be connected to MCLK of DSP. Set up the jumper pins.
JP3 LRCK2
JP4 BICK2
JP5 MCLK
JP6 BICK
JP7 LRCK
JP8 SDTO
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(2-2) PLL Reference Clock : BICK or LRCK pin
AK4371
MCKI MCKO BICK LRCK SDATA 32fs or 64fs 1fs BCLK LRCK
DSP or P
SDTO
Figure 4. PLL Master Mode (PLL Reference Clock : BICK or LRCK pin)
PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR). BICK,LRCK and SDATA are supplied from PORT2. Set up the jumper pins.
JP3 LRCK2
JP4 BICK2
JP5 MCLK
JP6 BICK
JP7 LRCK
JP8 SDTO
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(3) External Slave Mode The AK4371's register should be set to EXT Slave Mode. MCKI frequency should be set to the same as the specification of DSP or DIR. About the AK4371's register definitions, refer to datasheet of the AK4371.
AK4371
MCKO MCKI BICK LRCK SDATA 256fs, 384fs, 512fs, 768fs or 1024fs 32fs ~ 64fs 1fs
DSP or P
MCLK BCLK LRCK SDTO
Figure 5. External Slave Mode
(3-1) Evaluation using DIR (Optical Link) of AK4116 PORT1 (DIR) is used. Nothing should be connected to PORT2(DSP). Set up the jumper pins.
JP3 LRCK2
JP4 BICK2
JP5 MCLK
JP6 BICK
JP7 LRCK
JP8 SDTO
(3-2) Evaluation connecting AKD4371 with external DSP PORT2 (DSP) is used. Nothing should be connected to PORT1(DIR). Set up the jumper pins.
JP3 LRCK2
JP4 BICK2
JP5 MCLK
JP6 BICK
JP7 LRCK
JP8 SDTO
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(4) External Master Mode The AK4371's register should be set to EXT Master Mode. MCKI frequency should be set to the same as DSP's specification. About the AK4371's register definitions, refer to datasheet of the AK4371.
AK4371
MCKO MCKI BICK LRCK SDATA 256fs, 384fs, 512fs, 768fs or 1024fs 32fs, 64fs 1fs
DSP or P
MCLK BCLK LRCK SDTO
Figure 6. EXT Master Mode PORT2 (DSP) is used. Nothing should be connected to PORT1 (DIR). The system clock should be connected to MCLK of PORT2. SDTI of PORT2 should be connected to SDTO of DSP. The JP4(LRCK2) and JP3(BICK2)'s right side should be connected to LRCK and BICK of DSP. Set up the jumper pins.
JP3 LRCK2
JP4 BICK2
JP5 MCLK
JP6 BICK
JP7 LRCK
JP8 SDTO
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Other jumper pins set up
JP1 (GND) : Analog ground and Digital ground. OPEN : Separated. SHORT : Common. JP11 (INLN) : Setting of AK7832 Input pin "INLN". OPEN : When SW2 (SPK_PDN) is "L". SHORT : When SW2 (SPK_PDN) is "H". JP12 (INRN) : Setting of AK7832 Input pin "INRN". OPEN : When SW2 (SPK_PDN) is "L". SHORT : When SW2 (SPK_PDN) is "H". JP13 (DVDD_REG) : Setting of Power Supply "DVDD". OPEN : It supplies "DVDD" from the outside. SHORT : It supplies "DVDD" from the Regulator (3.3V).
The function of the toggle SW
Upper-side is "H" and lower-side is "L". [SW1] (DAC/DIR_PDN): Power down of AK4371 and AK4116. Keep "H" during normal operation. [SW2] (SPK_PDN): Power down of AK7832. Keep "H" during normal operation.
Indication for LED
[LED1] (ERF): Monitor INT0 pin of the AK4116. LED turns on when some error has occurred to AK4116.
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Serial Control
The AK4371 can be controlled via the printer port (parallel port) of IBM-AT compatible PC. Connect PORT3 (uP -IF) with PC by 10 wire flat cable packed with the AKD4371.
Connect PC
CSN CCLK CDTI AKD4371
10 Wire Flat Cable 10pin Connector 10pin Header
Figure 7. Connect of 10 wire flat cable
(1) 3-wire Serial Control Mode
The jumper pins should be set to the followings.
JP10 CAD0 JP2 I2C_SEL JP9 SDA
I2C
3-wire
(2) I2C-bus Control Mode
The jumper pins should be set to the followings. (2-1) In case of using CAD0=0 (device address bits).
JP10 CAD0 JP2 I2C_SEL JP9 SDA
I2C
3-wire
(2-2) In case of using CAD0=1 (device address bits).
JP10 CAD0
JP2 I2C_SEL
JP9 SDA
I2C
3-wire
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Input / Output circuit
(1) Input Circuit LIN1/RIN1, LIN2/RIN2, LIN3/RIN3 Input circuits
C19 1u
6 4 3
J2 LIN1/RIN1
+ RIN1 + LIN1
C20 1u
J3 LIN2/RIN2
C21 1u
6 4 3
+ RIN2 + LIN2
C27 1u
J5 LIN3/RIN3
C29 1u
6 4 3
+ RIN3 + LIN3
C31 1u
Figure 8. LIN1/RIN1,LIN2/RIN2,LIN3/RIN3 Input circuits
(2)
Output Circuit 1) HPL/HPR Output Circuit
+ R9 (short) HPR
6
C25 100u J4
HPL
+
R10(short)
C28 100u
4 3
HP
Figure 9. HPL/HPR Output Circuit
2) MOUT Output Circuit
J1
+
C18 1u
6 4 3
MOUT
MOUT
Figure 10. MOUT Output Circuit
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3) LOUT/ROUT Output Circuit
ROUT R12 47k
6
+
C30 1u
R11 220
J6
LOUT R14 47k
+
C32 1u
R13 220
4 3
L/R OUT
Figure 11. LOUT/ROUT Output Circuit
4) Speaker Output Circuit Evaluation using AK7832's Speaker , the jumper pins should be set to the followings.
JP11 INLN
JP12 INRN
TP2 VCLN VCLN
1
6 4 3
J7
TP3 VCLP VCLP
1
SPP_L
TP4 VCRN VCRN
1
6 4 3
J8
TP5 VCRP VCRP
1
SPP_R
Figure 12. SPK-Amp Output Circuit
AKM assumes no responsibility for the trouble when using the above circuit examples.
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Control Software Manual Set-up of evaluation board and control software
1. Set up the AKD4371 according to previous term. 2. Connect IBM-AT compatible PC with AKD4371 by 10-line type flat cable (packed with AKD4371). Take care of the direction of 10pin header. (Please install the driver in the CD-ROM when this control software is used on Windows 2000/XP. Please refer "Installation Manual of Control Software Driver by AKM device control software". In case of Windows95/98/ME, this installation is not needed. This control software does not operate on Windows NT.) 3. Insert the CD-ROM labeled "AK4371 Evaluation Kit" into the CD-ROM drive. 4. Access the CD-ROM drive and double-click the icon of "AKD4371.exe" to set up the control program. 5. Then please evaluate according to the follows.
Operation flow
Keep the following flow. 1. Set up the control program according to explanation above. 2. Click "Port Reset" button. 3. Click "Write default" button
Explanation of each buttons
1. 2. 3. 4. 5. 6. 7. 8. [Port Reset] : [Write default] : [All Write] : [Function1] : [Function2] : [Function3] : [Function4] : [Function5] : Set up the USB interface board (AKDUSBIF-A) when using the board. Initialize the register of AK4371. Write all registers that is currently displayed. Dialog to write data by keyboard operation. Dialog to write data by keyboard operation. The sequence of register setting can be set and executed. The sequence that is created on [Function3] can be assigned to buttons and executed. The register setting that is created by [SAVE] function on main window can be assigned to buttons and executed. Save the current register setting. Write the saved values to all register. Dialog to write data by mouse operation.
9. [SAVE] : 10. [OPEN] : 11. [Write] :
Indication of data
Input data is indicated on the register map. Red letter indicates "H" or "1" and blue one indicates "L" or "0". Blank is the part that is not defined in the datasheet.
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Explanation of each dialog 1. [Write Dialog]: Dialog to write data by mouse operation
There are dialogs corresponding to each register. Click the [Write] button corresponding to each register to set up the dialog. If you check the check box, data becomes "H" or "1". If not, "L" or "0". If you want to write the input data to AK4371, click [OK] button. If not, click [Cancel] button.
2. [Function1 Dialog] : Dialog to write data by keyboard operation
Address Box: Data Box: Input registers address in 2 figures of hexadecimal. Input registers data in 2 figures of hexadecimal.
If you want to write the input data to AK4371, click [OK] button. If not, click [Cancel] button.
3. [Function2 Dialog] : Dialog to evaluate DATT
There are dialogs corresponding to register of 05h , 06h , 09h , 0Eh and 13h. Address Box: Input registers address in 2 figures of hexadecimal. Start Data Box: Input starts data in 2 figures of hexadecimal. End Data Box: Input end data in 2 figures of hexadecimal. Interval Box: Data is written to AK4371 by this interval. Step Box: Data changes by this step. Mode Select Box: If you check this check box, data reaches end data, and returns to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 09 08 07 06 05 04 03 02 01 00 If you do not check this check box, data reaches end data, but does not return to start data. [Example] Start Data = 00, End Data = 09 Data flow: 00 01 02 03 04 05 06 07 08 09 If you want to write the input data to AK4371, click [OK] button. If not, click [Cancel] button.
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4. [SAVE] and [OPEN] 4-1. [SAVE] All of current register setting values displayed on the main window are saved to the file. The extension of file name is "akr". (1) Click [SAVE] Button. (2) Set the file name and click [SAVE] Button. The extension of file name is "akr". 4-2. [OPEN] The register setting values saved by [SAVE] are written to the AK4371. The file type is the same as [SAVE]. (1) Click [OPEN] Button. (2) Select the file (*.akr) and Click [OPEN] Button.
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5. [Function3 Dialog]
The sequence of register setting can be set and executed. (1) Click [F3] Button. The default setting sequence DAC->HP(3D=OFF) is displayed. Jump to (3) below if the default setting sequence is used. Go to (2) if the other setting sequence is required. (2) Set the control sequence. Set the address, Data and Interval time. Set "-1" to the address of the step where the sequence should be paused. (3) Click [START] button. Then this sequence is executed. The sequence is paused at the step of Interval="-1". Click [START] button, the sequence restarts from the paused step. This sequence can be saved and opened by [SAVE] and [OPEN] button on the Function3 window. The extension of file name is "aks".
Figure 13. Window of [F3]
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6. [Function4 Dialog]
The sequence file (*.aks) saved by [Function3] can be listed up to 10 files, assigned to buttons and then executed. When [F4] button is clicked, the window as shown in Figure 9 opens.
Figure 14. [F4] window
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6-1. [OPEN] buttons on left side and [START] buttons (1) Click [OPEN] button and select the sequence file (*.aks) saved by [Function3]. The sequence file name is displayed as shown in Figure 10. ( In case that the selected sequence file name is "DAC_Stereo_ON.aks")
Figure 15. [F4] window (2) (2) Click [START] button, then the sequence is executed.
6-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of sequence file displayed on [Function4] window can be saved to the file. The file name is "*.ak4". [OPEN] : The name assign of sequence file(*.ak4) saved by [SAVE] is loaded.
6-3. Note (1) This function doesn't support the pause function of sequence function. (2) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (3) When the sequence is changed in [Function3], the sequence file (*.aks) should be loaded again in order to reflect the change.
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7. [Function5 Dialog]
The register setting file(*.akr) saved by [SAVE] function on main window can be listed up to 10 files, assigned to buttons and then executed. When [F5] button is clicked, the window as shown in Figure 11 opens.
Figure 16. [F5] window
7-1. [OPEN] buttons on left side and [WRITE] button (1) Click [OPEN] button and select the register setting file (*.akr). The register setting file name is displayed as shown in Figure 12. (In case that the selected file name is "DAC_Output.akr") (2) Click [WRITE] button, then the register setting is executed.
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Figure 17. [F5] window (2) 7-2. [SAVE] and [OPEN] buttons on right side [SAVE] : The name assign of register setting file displayed on [Function5] window can be saved to the file. The file name is "*.ak5". [OPEN] : The name assign of register setting file(*.ak5) saved by [SAVE] is loaded.
7-3. Note (1) All files used by [SAVE] and [OPEN] function on right side need to be in the same folder. (2) When the register setting is changed by [SAVE] Button on the main window, the register setting file (*.akr) should be loaded again in order to reflect the change.
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MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * MCLK * BICK * fs * Bit * Measurement Mode * Power Supply * Measurement Filter * Temperature : Audio Precession System Two Cascade : 11.2896MHz : 64fs : 44.1kHz : 24bit : EXT Slave Mode : AVDD = HVDD = DVDD = PVDD = 3.3V :22Hz 20kHz : Room
Parameter DAC Analog Output Characteristics DAC -> HP AMP (RL=16) THD+N (0dBFS Output) D-Range (-60dB Output, A-weighted) S/N (A-weighted) DAC -> LOUT (RL=47k) THD+N (0dBFS Output) D-Range (-60dB Output, A-weighted) S/N (A-weighted)
Result (Lch / Rch) 54.1 / 54.1 92.7 / 92.7 93.0 / 93.0 59.8 / 60.0 90.2 / 90.3 90.2 / 90.3
Unit dB dB dB dB dB dB
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[Plot of Headphone Amp]
AKM
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 -120
HP-AMP THD + N vs Input Level fs=44.1kHz , fin=1kHz
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 18. THD+N vs. Input Level
AKM
+0 -10 -20 -30 -40 -50 d B r A -60 -70 -80 -90 -100 -110 -120 -130 -140 20
HP-AMP THD + N vs Input Frequency fs=44.1kHz , 0dB Input
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 19. THD+N vs. Input Frequency
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AKM
+0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120 -120
HP-AMP Linearity fs=44.1kHz , fin=1kHz
d B r A
-110
-100
-90
-80
-70
-60 dBFS
-50
-40
-30
-20
-10
+0
Figure 20. Linearity
AKM
+2 -0 -2 -4 -6 -8 d B r A -14 -16 -18 -20 -22 -24 20 -10 -12
HP-AMP Frequency Response fs=44.1kHz , 0dB Input
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 21. Frequency Response (including external HPF) - 22 2007/07
[AKD4371-B]
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B r A -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200
HP-AMP FFT fs=44.1kHz , 0dB Input
500 Hz
1k
2k
5k
10k
20k
Figure 22. FFT Plot(1kHz,0dB)
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B r A -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200
HP-AMP FFT fs=44.1kHz , -60dB Input
500 Hz
1k
2k
5k
10k
20k
Figure 23. FFT Plot(1kHz,-60dB)
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AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B r A -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200
HP-AMP FFT fs=44.1kHz , No Signal
500 Hz
1k
2k
5k
10k
20k
Figure 24. FFT Plot(Noise Floor)
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B r A -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100 200
HP-AMP FFT fs=44.1kHz , Outband Noise
500
1k Hz
2k
5k
10k
20k
50k
100k
Figure 25. Out-band Noise
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AKM
+0 -10 -20 -30 -40 -50 d B -60 -70 -80 -90 -100 -110 -120 20
HP-AMP Crosstalk fs=44.1kHz , 0dB Input
50
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 26. Crosstalk
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REVISION HISTORY
Date (yy/mm/dd) 06/12/12 07/07/24 Manual Revision KM086200 KM086201 Board Revision 0 1 Reason First Edition Change Change Page Contents
27
C12 4.7nF 47nF Device revision was changed. Rev. A
Rev. B
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
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A
B
C
D
E
RIN1
RIN3
RIN2
LIN1
LIN3
LIN2
DGND
E
JP1 GND
AGND
E
HPL HPR
31
29
32
30
28
27
26
U1
RIN1
RIN3
RIN2
LIN1
LIN3
LIN2
HPL
R1 SDATA R2 BICK
D
51
1 SDATA VSS1 24
HPR
25
51
2 BICK HVDD 23
R3 LRCK R4 MCKI R5 DVDD
51
3 LRCK AVDD 22
51
4 MCKI VCOM 21
10
5
+ AVDD_REG + 10u C10
10u C8 C11 0.1u
C9 0.1u
6
DVDD
AK4371VN
C7 0.22u
VREF 20
PVDD
ROUT
19
7
VCOC
LOUT
18
CSN/CAD0
CCLK/SCL
CDTI/SDA
C
MUTET
C12 47n R6 10k
8
VSS2 MCKO VSS3
MOUT PDN
17
MOUT C13 0.1u
B2 B1 A5 A2
I2C
10
11
12
13
14
15
16
U2 1u C14
INRP
SCL
A3
INRN
NC
+ TP1 MCKO
1
B3
INLN
NC
A1
9
R7 51 C16
B
CDTI
CCLK
CSN
PDN
JP2 I2C_SEL R8 47k
SPK_PDN
I2CEN
VCRN
VDD3
VDD2
C4
C5
D1
D2
D3
D4
VCLN
VSS2
A
A
B
C
+ +
C5 0.1u
+ +
C3 0.1u
+ + HVDD_REG C4 10u
D
C1 0.1u
C2 10u
AVDD_REG 2.2u C6
ROUT
LOUT JP11 INLN JP12 INRN
C
C15 0.1u
INLP
NC
E5
B4
VSS3
VCLP
E4
VCLP
B5
VC
VSS1
E3
VCLN
C17 0.1u
0.01u
C1 DVDDI
AK7832
VCRP
E2
B
C2
SDA
NC
E1
C3
PDN
VDD1
D5
VCRP
VCRN D_REG
A
Title Size
AKD4371-B
Document Number
A3
Date:
D
AK4371 , AK7832
Sheet
E
Rev
1 3
Friday, August 10, 2007
1
of
A
B
C
D
E
E
E
VCC +5V J2 LIN1/RIN1
6
+
C19 1u C20 1u
C18 1u
J1
6 4 3
+ RIN1 + MOUT
L1 10u
1 1 2
D_REG DIR_REG HVDD_REG AVDD_REG JP13 DVDD DVDD_REG J3 LIN2/RIN2
L2 (short)
2
4 3
MOUT LIN1
T1 TA48M33F
GND IN OUT
L3 (short)
1 1 2
L4 (short)
2
C21 1u
6 4 3
+ C22 47u
D
C23 0.1u
C24 0.1u
+ C26 47u
RIN2 C27 1u + LIN2
HPR
6
+
R9 (short)
C25 100u J4 C28 100u
4 3
D
HPL J5 LIN3/RIN3
6 4 3
+
+ + RIN3 ROUT LIN3 + LOUT
R10(short)
HP
C29 1u C31 1u
+
C30 1u R12 47k
R11 220
J6
6
+
C32 1u R14 47k
R13 220
4 3
L/R OUT
C
C
TP2 VCLN VCLN
1 6
J7
4 3
TP3 VCLP VCLP
1
SPP_L
TP4 VCRN
B
J8
6
B
VCRN
1
TP5 VCRP VCRP
1
4 3
SPP_R
A
A
Title Size
AKD4371-B
Document Number
A3
Date:
A B C D
Input/Output
Sheet
E
Rev
1 2
of
Friday, August 10, 2007
3
A
B
C
D
E
E
E
D_REG C33 0.1u
1
D_REG L5 47u
A 2
LED1
K
R15 1k
PORT1
VCC GND OUT 3 2 1
ERF C34 0.1u
1 2 3 4 5 6 14
1A 1Y 2A 2Y 3A 3Y Vcc GND
4Y 4A 5Y 5A 6Y 6A
8 9 10 11 12 13
SPK_PDN
PDN C36 10u DIR_REG + C35 0.1u
TORX141
7
K
D
K
U3 74HC14
D1 HSU119
R16 10k
D2 HSU119
R17 10k
D
A
R18 470
C37 0.1u L
H
3 1
L
3
A
H
1
R19 12k
SW1 DAC/DIR_PDN
2 18 17 19 16
C38 SW2 0.1u SPK_PDN
2
C39 0.1u
U4
20
AVSS
R
AVDD
PDN
1
INT0
RX0
INT1
15
R20 5.1 DIR_REG + 10u C40 C41 0.1u TP6 XTI
2 DVDD CSN 14
CSN
3
DVSS
C
11
C42 10p C43 10p
AK4116
CCLK
13
CCLK U5
C
4
XTI
CDTI
12
CDTI
3 A1 B1 21
X1 11.2896MHz
2 5 XTO CDTO 11
CDTO
4 A2 B2 20
PDN
SDATA JP3 LRCK2
MCKO
SDTO
DAUX
LRCK
BICK
5
A3
B3
19
6
7
8
9
10
LRCK JP4 BICK2
6
A4
B4
18
BICK
JP5
7 A5 B5 17
MCKI
MCLK JP6 BICK
9 8 A6 B6 16
CSN
JP7 LRCK
B
A7
B7
15
CCLK
10
A8
B8
14
B
JP8 SDTO D_REG C44 0.1u PORT2 MCLK BICK LRCK SDTI
1 2 3 4 5 10 9 8 7 6
GND GND
1
VCCA
VCCB
24
DVDD
2
DIR
VCCB
23
11
D_REG
R21 R23 R25
10k 10k 10k
R22 R24 R26
470 470
12
GND
OE
22
C45 0.1u
470
GND
GND
13
DSP D_REG R27 10k
1 2 3 4 5
A
74AVC8T245 PORT3
10 9 8 7 6
CSN SCL/CCLK SDA/CDTI CDTO
CDTI CDTO JP10 CAD0 JP9 SDA
A
uP-I/F
Title Size
AKD4371-B
Document Number
A2
Date:
A B C D
CLOCK
Sheet
Rev
1 3
of
Friday, August 10, 2007
E
3

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